1. Field of the Invention
The present invention relates generally to chemical mechanical polishing (CMP) systems, and to techniques for improving the performance and effectiveness of CMP operations. More specifically, the present invention relates to apparatus and methods for consistently releasably securing a wafer to and releasing the wafer from a CMP carrier, while reducing interference by such apparatus and methods with CMP operations performed on the wafer.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including polishing, buffing and wafer cleaning; and to perform wafer handling operations in conjunction with such CMP operations. For example, a typical semiconductor wafer may be made from silicon and, for example, may be a disk that is 200 mm or 300 mm in diameter. The 200 mm wafer may have a thickness of 0.028 inches, for example. For ease of description, the term xe2x80x9cwaferxe2x80x9d is used below to describe and include such semiconductor wafers and other planar structures, or substrates, that are used to support electrical or electronic circuits.
Typically, integrated circuit devices are in the form of multi-level structures fabricated on such wafers. At the wafer level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. Patterned conductive layers are insulated from other conductive layers by dielectric materials. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization.
In a typical CMP system, a wafer is mounted on a carrier with a surface of the wafer exposed for CMP processing. The carrier and the wafer rotate in a direction of rotation. The CMP process may be achieved, for example, when the exposed surface of the rotating wafer and an exposed surface of a polishing pad are urged toward each other by a force, and when such exposed surfaces move in respective polishing directions. For wafer handling after completion of one step of the CMP processing, a vacuum may be applied to the carrier to retain the wafer on the carrier as the carrier and the wafer are moved to a next CMP processing station. Upon completion of the CMP processing using that carrier, pressure may be applied to the carrier in a xe2x80x9cblow offxe2x80x9d operation to force the wafer from the carrier.
A situation has been encountered in providing apparatus and methods for retaining the wafer on the carrier during such carrier/wafer movement, and in providing the blow off pressure to the carrier to force the wafer from the carrier. This situation is described with reference to FIG. 1A, which shows a plan view looking upwardly to a typical prior carrier 20. The carrier 20 is a disk-like structure having a diameter in excess of seven inches and a flat surface 21 that provides support for a protective carrier film 22 which supports a wafer 23 during the CMP processing. In FIG. 1A, the wafer 23 is shown cut away to expose the film 22, and the film 22 is shown cut away to expose the carrier 20. An exemplary six to twenty holes are typically formed through the carrier 20. In FIG. 1A, six holes 24 are illustrated, each about 0.040 inches in diameter and typically formed through the prior carrier 20 at locations L1 through L6 across the flat surface 21 as shown in cross section in FIG. 1B. As described below, locations L1 through L6 are widely spaced.
In one embodiment of the prior carrier 20, each of the holes 24 is centered on a circular line 26 having a diameter of between six and seven inches. The circular line 26 is coaxial with a center 27 of the prior carrier 20. Around the circular line 26, uniform spacing of each one of the six holes 24 from all other of the holes may be about three and one-half inches, which is defined as xe2x80x9cwidely spacedxe2x80x9d and across the diameter of the circular line 26 the hole-to-hole spacing may exceed six inches, which is within the definition of xe2x80x9cwidely spacedxe2x80x9d. In such embodiment, the flat surface 21 of the prior carrier 20 is typically protected using a consumable layer in the form of the carrier film 22 having a thickness of about 0.020 inches and a diameter corresponding to the diameter of the prior carrier 20. The carrier film 22 overlies the flat surface 21. The carrier film 22 is provided with six punched holes 28 each having a diameter of about 0.060 inches. The carrier film holes 28 are centered on a similar circle having a diameter of between six and seven inches. Each carrier film hole 28 is coaxial (i.e., aligned) with the center of a corresponding one the six carrier film holes 24.
With such background in mind, the situation that has been encountered relates to the following. Although the exemplary six carrier holes 24 and the exemplary six aligned carrier film holes 28 generally provide enough vacuum to the wafer 23 for retaining the wafer 23 on the prior carrier 20 during such carrier/wafer movement, and for applying the blow off pressure to the wafer 23 on the prior carrier 20, when such prior carrier 20 and carrier film 22 are used with the wafer 23 in CMP operations, undesired deformation of the wafer 23 occurs. For example, FIGS. 1C and D depict results of examining a surface 29 of the wafer 23 that was exposed to a CMP polishing pad 36 (FIG. 1B) during a CMP operation using the prior carrier 20 and carrier film 22 described above. FIG. 1C graphically shows percent removal rate plotted against the locations L1 through L6 at which the carrier holes 24 and the carrier film holes 28 are spaced around the circle 26. The removal rate is the rate at which CMP occurs on the exposed surface 29, and may be measured in Angstrom units, for example. Although a 100% polishing removal rate is desired on the entire area of the exposed wafer surface 29, FIG. 1C shows that there is a decrease (or reduction) of up to 15% in the percent removal rate. FIG. 1D shows that such decrease corresponds to low removal rate portions 31 of the exposed area 29 (centered at the aligned holes 24 and 28 at locations L1 through L6 on the wafer 23). The portions 31 of the exposed surface 29 of the wafer 23 corresponding to the decreased polishing removal rate may also be referred to as xe2x80x9clow polish-rate areasxe2x80x9dand are depicted in FIG. 1D by many circular lines 32 centered at the centers of the respective coaxial holes 24 and 28. The outer circular lines 33 are shown having diameter exceeding that of both of the respective holes 24 and 28 to illustrate that the low polish rate areas extend radially from such centers to distances greater than the diameter of the largest (i.e., the carrier film) hole 28. Thus, there is an effect, termed a xe2x80x9cfield effectxe2x80x9d, of reduced percent removal rate having a diameter significantly exceeding the diameter of the larger (carrier film) holes 28. The low polish-rate areas, or portions, 31 of the exposed surface 29 of the wafer 23 may have a diameter of up to about one inch, for example. These low polish-rate areas may be unusable for fabricating silicon devices, add to manufacturing costs due to a need to locate such portions, and reduce the yield of the polished wafers.
This situation relating to the low polish rate areas 31 is complicated by the ongoing need to provide a way for vacuum and pressure to be applied from the prior carrier 20 through the carrier film 22 to the wafer 23 for the above-noted necessary wafer handling operations. Since these wafer handling operations are necessary, in the past it has not been acceptable to use a carrier 20 without such six to twenty holes 24. However, a problem is that the cause of the low percent removal rate portions 31 has not been apparent. Thus, currently, although the low percent removal rate portions 31 are produced on the wafer 23, such prior carriers 20 and prior carrier films 22, each having the respective six to twenty aligned holes 24 and 28, are still in commercial use.
What is needed then, is an identification of the cause of the low polish rate areas 31, coupled with a solution, such that a CMP system would be provided in which apparatus and methods furnish both the necessary vacuum and pressure from the carrier through the carrier film to the wafer without interfering with the desired planarization of the wafer during CMP operations. Moreover, since the desired CMP operations must apply the CMP force against the exposed surface of the wafer to polish that exposed surface, what is needed is an identification of such cause, and a solution defining a way to apply such CMP force without having portions of the wafer experience reduced removal rates
Broadly speaking, the present invention fills these needs by identifying the cause of the low polish-rate areas, and by providing CMP systems and methods which implement solutions to the above-described problems. Thus, by the present invention, both the necessary vacuum and pressure may be applied from a vacuum chuck of the carrier through a carrier film to the wafer without interfering with the desired planarization of the wafer during CNP operations. The present invention identifies, as the cause of the low polish rate-areas on the wafer, non-uniform compression of the carrier film in response to a force from the wafer on the carrier film during the CMP operations. The present invention eliminates the cause of the low removal rate portions by CMP apparatus and methods that uniformly compress the carrier film in response to a force from the wafer on the carrier film during the CMP operations.
In the present invention, one aspect of achieving the uniform carrier film compression is significantly reducing the distance between adjacent holes of the carrier film. Another aspect of the present invention involves coordinating the locations of such holes and reducing the diameter of the holes in the carrier film. In this manner, the compression of the carrier film is significantly more uniform as evidenced by elimination of the low removal rate portions 31.
In another aspect of the present invention, the configurations of the carrier film and of the vacuum chuck structures are coordinated to provide such solutions. The vacuum chuck has opposite first and second surfaces. The first surface defines a first mounting area. The vacuum chuck has a rigid porous structure extending between the first and second surfaces adjacent to substantially all of the first mounting area. The carrier film has a third surface configured to engage a wafer, and has a fourth surface configured to engage the first surface of the vacuum chuck. The carrier film has an array of holes extending across substantially all of the fourth surface. Each of the holes extends from the third surface to the fourth surface. Such structural coordination is that each of the holes overlaps the rigid porous structure of the ceramic material upon engagement of the fourth surface of the carrier film with the first surface of the vacuum chuck.
In yet another aspect of the invention, the coordination of the configurations of structures of the wafer carrier film and of the vacuum chuck is provided to reduce the effects of the structures on chemical mechanical polishing operations performed on the wafer mounted on the structures. The carrier film has a first surface configured to engage the wafer and a second surface configured with a pressure transfer area. The carrier film has a uniform two-dimensional arrangement of holes extending completely across the vacuum transfer area. Each of the holes extends along a third dimension between the first and second surfaces. Each of the holes of the uniform two-dimensional arrangement of holes is aligned with at least one passage through the vacuum chuck by structure of the vacuum chuck that is in engagement with the pressure transfer area. The vacuum chuck structure is rigid and porous, defined by sintered ceramic material having micropores.
In a related aspect of the present invention, each hole in the uniform two-dimensional arrangement of holes in the carrier film has a diameter of from about 0.005 +or xe2x88x920.002 inches to about 0.020 +or xe2x88x920.002 inches and the array spaces one hole from many adjacent holes by a distance of about 0.060 to 0.250 inches.
In still another aspect of the invention, a method of manufacturing a wafer carrier film and a vacuum chuck is provided for reducing the effects of the film and the chuck on chemical mechanical polishing operations performed on the wafer mounted on the film. Operations of the method may include providing the vacuum chuck having opposite first and second surfaces. The first surface defines a first mounting area, and the vacuum chuck has a rigid porous structure extending between the first and second surfaces adjacent to substantially all of the first mounting area. In another operation, there is provided a carrier film having a third surface configured to engage the wafer and a fourth surface configured to engage the first surface of the vacuum chuck. The carrier film is provided with an array of holes extending across substantially all of the fourth surface. Another operation engages the first mounting area with the fourth surface of the carrier film to cause each of the holes of the array to overlap the rigid porous structure of the ceramic material.
A further aspect of the present invention relates to the operation of providing the carrier film, which provides the array of holes in a uniform geometric pattern. The uniform geometric pattern may be defined by equilateral triangles, or may be defined by a grid of orthogonally arranged lines, wherein the locations of the holes are defined by intersections of the lines.
Yet another aspect of the present invention relates to apparatus for positioning a wafer for chemical mechanical polishing operations. A housing has a manifold for distributing gas at a range of pressures from a vacuum to positive pressure. A vacuum chuck is mounted on the housing overlying the manifold for receiving the range of pressures. The vacuum chuck has a structure configured with a flat mounting section having a mounting area and comprising micropores extending across substantially all of the mounting area. Groups of the micropores provide continuous passageways extending generally perpendicular to the flat mounting section. A carrier film is mounted on the vacuum chuck and has a first surface configured to engage a wafer and a second surface configured to engage substantially all of the mounting area. The carrier film may have about 100 holes per square inch of the second surface. The holes extend from the first surface to the second surface in a two-dimensional uniform pattern extending across the entire second surface. Each of the holes may be overlapped by at least one group of the micropores of the ceramic material when the mounting area of the vacuum chuck engages the second surface of the carrier film. The overlapped relationship aligns each hole of the carrier film with the continuous passageway defined by the at least one group of micropores. With the passageways of the vacuum chuck aligned with the holes of the carrier film, and with the exemplary about 100 holes per square inch of the second surface of the carrier film providing the holes located at aligned locations that are very close together, the effect of the CMP force pressing the CMP polishing pad and the wafer against each other is significantly different from that of the prior art described above, and does not interfere with the desired planarization of the wafer during CMP operations.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.